Analog filter architecture

ABSTRACT

According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.

BACKGROUND

[0001] Small electronic circuits are often used in conjunction withhigh-frequency signals. However, some transmission materials used inthese circuits cause significant signal loss when carrying highfrequency signals. For example, signals transmitted at 3 to 4 GHz over asmall portion of FR4 substrate may experience 30 to 40 dB of signalloss.

[0002] Circuit designers attempt to compensate for this loss byfiltering received signals. In one example, received signals areconverted to digital signals with an analog-to-digital converter andthen filtered using a digital filter. Analog-to-digital converters are,however, often costly and difficult to implement at high data rates.Even if analog-to-digital conversion is not problematic for a givenhigh-frequency application, subsequent filtering of the digitalhigh-frequency signals may itself be difficult to design and/orimplement.

[0003] Analog filters may be used to address the foregoing, but powerrequirements of these filters usually increase with signal frequency.For example, conventional Finite Impulse Response (FIR) analog filtersoperate by convolving samples of a received signal with a set ofweighting coefficients. A finite state machine typically performs theconvolution by rotating the coefficients amongst a set of multipliersfor multiplying a fixed signal sample by a weighting coefficient and/orby rotating the signal samples amongst a set of multipliers formultiplying a signal sample by a fixed weighting coefficient. The finitestate machine as well as other elements used to perform the convolutionadds significantly to the power requirements of the FIR filter,particularly during high-frequency operation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004]FIG. 1 is a diagram of a voltage-to-current converter according tosome embodiments.

[0005]FIG. 2 is a diagram of a weighting unit according to someembodiments.

[0006]FIG. 3 is a diagram illustrating elements of a filter according tosome embodiments.

[0007]FIG. 4 is a diagram illustrating elements of a filter according tosome embodiments.

[0008]FIG. 5 is a diagram illustrating timings according to someembodiments.

[0009]FIG. 6 is a diagram illustrating elements of a weighting circuitaccording to some embodiments.

[0010]FIG. 7 is a diagram illustrating elements of a filter according tosome embodiments.

[0011]FIG. 8 is a block diagram of a system according to someembodiments.

DETAILED DESCRIPTION

[0012]FIG. 1 is a circuit-level diagram of voltage-to-current converter1 according to some embodiments. Voltage-to-current converter 1 isadapted to receive a differential-mode voltage signal represented bydifferential voltage signals V_(data) and V_(data#). Embodiments of thepresent invention may operate in conjunction with other signaling modes,including single-ended and pseudo-differential.

[0013] Voltage-to-current converter 1 includes bias current source 2coupled to parallel loads 3 and 4, which may comprise resistors. Loads 3and 4 are respectively coupled to a source of p-channel metal oxidesemiconductor (PMOS) transistor 5 and to a source of PMOS transistor 6.Voltage signal V_(data) is applied to a gate of transistor 5 andV_(data#) is applied to a gate of transistor 6. By virtue of thisconfiguration, voltage-to-current converter 1 converts voltage signalV_(data) to differential current signal I_(data) and outputs I_(data)from a drain terminal of transistor 6. Similarly, converter 1 convertsvoltage signal V_(data#) to differential current signal I_(data#) andoutputs I_(data#) from a drain terminal of transistor 5. In a case thatconverter 1 performs a substantially linear conversion, differentialcurrent signals I_(data) and I_(data#) together represent a currentsignal that substantially encodes any data encoded by thedifferential-mode voltage signal represented by differential voltagesignals V_(data) and V_(data #).

[0014]FIG. 2 illustrates voltage-to current converter 1 and elements ofweighting unit 10 according to some embodiments. Weighting 10 is adaptedto modulate differential current signals I_(data) and I_(data#) receivedfrom converter 1 based on one-bit control signals D₁ and D₂.Accordingly, weighting 10 may be characterized as a current-steeringdigital-to-analog converter.

[0015] As shown, current signal I_(data) is applied to source terminalsof PMOS transistors 11 through 14 and current signal I_(data#) isapplied to source terminals of PMOS transistors 15 through 18. Controlsignals D₁ and D₂ are applied as shown to base terminals of transistors11 through 18, wherein {overscore (Di)} denotes the Boolean complementof Di. The weights applied to current signals I_(data) and I_(data#) aretherefore determined by control signals D₁ and D₂ and the relativechannel width-to-length ratios of transistors 11 through 18. Forexample, when D₁ and D₂ are both HIGH, signals received from converter 1are shunted to ground and the effective multiplication value, orweighting, is zero.

[0016] In the illustrated embodiment, the channel width-to-length ratioof transistors 13 through 16 is twice the channel width-to-length ratioof transistors 11, 12, 17 and 18. Therefore, the effectivemultiplication value is one in a case that D₁ is LOW and D₂ is HIGH, twoin a case that D₁ is HIGH and D₂ is LOW, and three in a case that bothD₁ and D₂ are LOW. Although weighting 10 of FIG. 2 utilizes two one-bitcontrol signals (or one two-bit signal), some embodiments may operate inconjunction with control signals of other bit lengths. Also, theabove-described channel width-to-length ratios need not be based onpowers of two.

[0017] The combination of voltage-to-current converter 1 and weighting10 realizes a weighting of the input differential-mode voltage signalrepresented by differential voltage signals V_(data) and V_(data#).Several of these combinations may be implemented in conjunction with oneanother to yield a simple filter that can be used within a more-complexfilter according to some embodiments.

[0018]FIG. 3 illustrates one embodiment of such a filter. Filter 20includes input ports 25 a and 25 b and filter taps a through d. Each oftaps a through d comprises an instance of samplers 30,voltage-to-current converter 1, weighting unit 10 and sign element 35.

[0019] Input ports 25 a and 25 b receive a differential voltage signalfrom a transmission line. Samplers 30 a through 30 d sample thedifferential signal according to their respective control, or clock,signals clk_(a) through clk_(d). Samplers 30 a through 30 d each consistof two switches connected to respective capacitors. In operation, theswitches are closed upon receipt of a HIGH control signal, and areopened when the control signal is LOW. Accordingly, the capacitors ofeach of samplers 30 a through 30 d store a sample of the differentialvoltage signal to which the capacitor is connected while the controlsignal is HIGH.

[0020] As described with respect to FIG. 1, voltage-to-currentconverters 1 a through 1 d convert differential voltage signals V_(data)and V_(data#) to differential current signals I_(data) and I_(data#).Signals converted by converters 1 a through 1 d may differ depending ondifferences in the timing of the control signals input to samplers 30 athrough 30 d. That is, although converters 1 a through 1 d according tosome embodiments may be identical, the signal samples upon which theyoperate, and therefore their outputs, may differ.

[0021] Weighting units 10 a through 10 d modulate signals received fromrespective converters 1 a through 1 d based on respective weightingcoefficients w₁ through W₄. In a case that coefficients w₁, through W₄are two-bit signals, units 10 a through 10 d may be substantiallysimilar to 10 of FIG. 2. Each weighting unit is coupled to one of signelements 35 a through 35 c. Sign elements 35 a through 35 c may comprisetwo-by-two crossbar switches, and are used to effectively reverse thesign of one of weighting coefficients w₁ through W₄.

[0022] Current signals output from sign elements 35 a through 35 d aresummed by convergent signal lines and sunk into loads 40 a and 40 b.Voltages developed by these loads represent a filtered differentialvoltage signal that is input to differential evaluation circuit 50,which may comprise a differential latch. Circuit 50 effectively convertsthe differential voltage signal into a logic signal indicative ofwhether a “1” or a “0” was received from the transmission line. Inoperation, a control signal clk_(e) is transmitted to evaluation circuit50 at an appropriate timing in order to prepare circuit 50 to evaluatean incoming differential voltage signal.

[0023]FIG. 4 illustrates elements of a filter according to someembodiments. Filter 55 includes instances 20 a through 20 f of filter 20of FIG. 3, and instances 50 a through 50 f of evaluation circuit 50 ofFIG. 3. Each of filters 20 a through 20 f receives differential voltagesignals V_(data) and V_(data#) from input ports 25 a and 25 b.

[0024] Also shown in FIG. 4 are phase generator 60 and decoder 70. Phasegenerator operates to output control signals clk₁ through clk₆ accordingto some embodiments. The control signals illustrated in FIG. 4 aresingle-ended for the sake of clarity, but differential control signalsmay be used. The control signals may be identical, with consecutive onesof the signals equally out of phase from one another. Phase generator 60outputs six control signals in the present example, with each controlsignal associated with an equal signal period.

[0025] Decoder 70 receives output from each of evaluation circuits 50 athrough 50 f. Each output reflects a sum of weighted signal samples. Aswill be described below, only one output per signal period willrepresent a valid filtered output. Decoder 70 therefore is controlled todetermine the valid output in order to generate a filtereddifferential-mode signal corresponding to the differential-mode voltagesignal represented by voltage signals V_(data) and V_(data#).

[0026] Different sets of control signals are input to each of filters 20a through 20 f. More particularly, each tap a through d of each filter20 a through 20 f receives a control signal intended to effect aconvolution over time as shown in FIG. 5. The convolution is alsoimplemented by inputting appropriate ones of control signals clk₁through clk₆ to each of evaluation circuits 50 a through 50 f so thatthe circuits generate outputs once each sampler of an associated filterhas acquired a new signal sample to be modulated.

[0027] As shown in FIG. 5, evaluation circuit 50 requires one bit-cellof time to evaluate and yield an output signal. Although samplers 30 bthrough 30 d may acquire new signal samples while taps a through c,respectively, are modulating received signal samples, sampler 30 a alsorequires one bit-cell delay to acquire a new sample at high frequenciesin cases where the clock is running at one-half the data rate. As aresult, six (four+two) filters are used for this particular arrangement.Other numbers of filters may be used in this or another arrangement. Forexample, five filters may be used (and the “Acquire” state is not used)in a case that the clock is running at the data rate. Other arrangementsmay also incorporate evaluation and/or acquire states having a durationof less than one bit-cell.

[0028] The table below specifies an arrangement of control signals clk₁through clk₆ within the elements of FIG. 4 according to someembodiments. The table specifies the signal period, or bit-cell,associated with each control signal, the sampler of each filter to whicheach control signal is input, and the evaluation circuit to which eachcontrol signal is input. control filter filter filter filter filterfilter eval. signal bit-cell 20a 20b 20c 20d 20e 20f circuit clk₁ 1, 7,. . . 30a — — 30d 30c 30b 50c clk₂ 2, 8, . . . 30b 30a — — 30d 30c 50dclk₃ 3, 9, . . . 30c 30b 30a — — 30d 50e clk₄ 4, 10, . . . 30d 30c 30b30a — — 50f clk₅ 5, 11, . . . — 30d 30c 30b 30a — 50a clk₆ 6, 12, . . .— — 30d 30c 30b 30a 50b

[0029]FIG. 6 illustrates a weighting circuit according to otherembodiments. As described with respect to filter 20, weighting circuit80 also receives differential voltage signals V_(data) and V_(data#)from input ports 25 a and 25 b. However, weighting circuit 80 includesone sampler 30 e controlled by one control signal clk_(e). Sampledsignals are converted by voltage-to-current converter 1 e andtransmitted to current mirror 90.

[0030] Current mirror 90 is comprised of n-channel metal oxidesemiconductor transistors and is adapted to generate four currentsignals substantially identical to the sampled differential currentsignals received from converter 1 e. According to some embodiments ofmirror 90, the generated signals are amplified versions of the receivedsignals. Current mirror 90 includes sign elements 95 through 98 that maybe used as described above to reverse the sign of a weightingcoefficient. In this regard, each of the four signals generated bymirror 90 is transmitted to one of weighting units 10 e through 10 h formodulation according to one of weighting coefficients w₁, through W₄.

[0031]FIG. 7 illustrates a filter composed of several instances ofweighting circuit 80. For purposes of clarity, the control signalsoutput by phase generator 60 and the signals output by weightingcircuits 80 a through 80 f are illustrated as single-ended signals. Eachof weighting circuits 80 a through 80 f receives a control signal fromphase generator 60. Instead of outputting a single summed signal to anassociated evaluation circuit 50 as shown in FIG. 4, each of weightingcircuits 80 a through 80 f outputs four weighted signals to fourdifferent ones of evaluation circuits 50 a through 50 f. Evaluationcircuits 50 a through 50 f and decoder 70 may operate as described withrespect to FIG. 5.

[0032] Numbers located adjacent to the output lines of weightingcircuits 80 a through 80 f indicate weighting coefficients applied tosignals carried by those lines. For example, the output line adjacent tothe number “3” of weighting circuit 80 d carries a signal modulatedaccording to weighting coefficient W₃. Since weighting circuit 80 dreceives control signal clk₄, the signal represents “X4*W3” according tothe notation of FIG. 5.

[0033] The FIG. 7 arrangement may therefore be used to implement thetimings shown in FIG. 5. The use of current mirror 90 within weightingcircuits 80 a through 80 f reduces a required number ofvoltage-to-current converters 1. Such a reduction may address powersupply headroom and power consumption issues.

[0034]FIG. 8 illustrates a block diagram of system 100 according to someembodiments. System 100 includes integrated circuit 102 comprisingsub-blocks such as arithmetic logic unit (ALU) 104, on-die cache 106 andfilter 55 of FIG. 4. Integrated circuit 102 may be a microprocessor oranother type of integrated circuit. Integrated circuit 102 may alsocommunicate with system memory 108 through filter 55, a host bus andchipset 110. According to some embodiments, integrated circuit 102 alsocommunicates with off-die cache 112 through filter 55. Other off-diefunctional units, such as graphics controller 114 and Network InterfaceController (NIC) 116, may communicate with integrated circuit 102 viaappropriate busses or ports.

[0035] Thus, embodiments may reduce power requirements by filteringusing fixed weighting coefficients and signal samples.

[0036] The several embodiments described herein are solely for thepurpose of illustration. For example, although the above embodiments aredescribed in conjunction with differential signaling, some embodimentsmay be used in conjunction with single-ended and/or pseudo-differentialsignaling. Samplers, voltage-to-current converters, current multipliers,sign elements and evaluation circuits other than those described abovemay be used in some embodiments, and each of these elements need not beidentical across and/or within weighting circuits. Moreover, theground-referenced PMOS transistors described herein may be substitutedwith V_(cc)-referenced n-channel metal oxide semiconductor transistors,and the current sources may be replaced with current sinks. Therefore,persons skilled in the art will recognize from this description thatother embodiments may be practiced with various modifications andalterations.

What is claimed is:
 1. A device comprising: a phase generator togenerate m control signals, each of the m control signals associatedwith a respective signal period; at least m filters, each of the atleast m filters comprising m-n taps, each of the m-n taps to receive oneof the m control signals, to acquire a signal sample according to asignal period associated with the received control signal, and tomodulate the signal sample according to a weighting coefficientassociated with the tap; and at least m evaluation circuits, eachcircuit associated with a respective one of the at least m filters andto output a sum of signal samples modulated by the taps of theassociated filter in response to one of the m control signals associatedwith a signal period other than the signal periods according to whichthe signal samples were acquired.
 2. A device according to claim 1wherein n is a sum of a number of signal periods for an evaluationcircuit to output the sum of weighted signal samples and a number ofsignal periods to acquire a signal sample.
 3. A device according toclaim 1, wherein a weighting coefficient associated with one tap of oneof the at least m filters is associated with one tap of each other ofthe at least m filters.
 4. A device according to claim 3, wherein aweighting coefficient associated with each tap of one of the at least mfilters is associated with one tap of each other of the at least mfilters.
 5. A device according to claim 1, wherein a control signal tobe received by one tap of one of the at least m filters is to bereceived by one tap of each other of the at least m filters.
 6. A deviceaccording to claim 5, wherein a control signal to be received by eachtap of one of the at least m filters is to be received by one tap ofeach other of the at least m filters.
 7. A device according to claim 1,wherein each of the m evaluation circuits is associated with arespective one of the m control signals.
 8. A device according to claim1, wherein in the case of a first control signal, one tap of each of m-nof the at least m filters is to receive the first control signal, toacquire a first signal sample according to a first signal periodassociated with the first control signal, and to modulate the firstsignal sample according to a weighting coefficient associated with theone tap.
 9. A device according to claim 8, wherein an evaluation circuitof one of the remaining n filters is to receive the first control signaland to output a first sum of weighted signal samples in response to thefirst control signal.
 10. A device according to claim 1, wherein each ofthe m signal periods is of equal duration.
 11. A device according toclaim 1, wherein each of the m-n taps of each of the at least m filterscomprises a voltage sampler, a voltage-to-current converter and aweighting unit to multiply a signal sample by an associated weightingcoefficient.
 12. A device comprising: a phase generator to generate mcontrol signals, each of the m control signals associated with arespective signal period; at least m weighting circuits, each of the atleast m weighting circuits associated with a respective one of the mcontrol signals, to acquire a signal sample according to a signal periodassociated with the respective one of the in control signals, andcomprising m-n weighting units, each of the m-n weighting units of oneof the at least m weighting circuits to modulate the acquired signalsample according to a weighting coefficient associated with the tap; andat least m evaluation circuits, each evaluation circuit to receive oneweighted signal sample from m-n weighting circuits and to output a sumof the received signal samples in response to one of the m controlsignals associated with a signal period other than the signal periodsaccording to which the signal samples were acquired.
 13. A deviceaccording to claim 12, wherein n is a sum of a number of signal periodsfor an evaluation circuit to output the sum of weighted signal samplesand a number of signal periods to acquire a signal sample.
 14. A deviceaccording to claim 12, wherein a weighting coefficient associated withone of the m-n weighting units of one of the at least m weightingcircuits is associated with one tap of each other of the at least mweighting circuits.
 15. A device according to claim 14, wherein aweighting coefficient associated with each of the m-n weighting units ofone of the at least in weighting circuits is associated with oneweighting unit of each other of the at least m weighting circuits.
 16. Adevice according to claim 12, wherein each of the m evaluation circuitsis associated with a respective one of the m control signals.
 17. Adevice according to claim 12, wherein each of the m signal periods is ofequal duration.
 18. A device according to claim 12, wherein each of theat least m weighting circuits comprises a voltage sampler, avoltage-to-current converter coupled to the voltage sampler, a currentmirror coupled to the voltage-to-current converter, and m-n weightingunits coupled to the current mirror, each of the m-n weighting units toreceive a substantially identical signal sample from the current mirrorand to multiply the signal sample by an associated weightingcoefficient.
 19. A method comprising: generating m control signals, eachof the m control signals associated with a respective signal period;receiving m-n of the m control signals with m-n taps of each of at leastm filters; acquiring, with each tap, a signal sample according to asignal period associated with the control signal received by the tap;modulating, with each tap, the signal sample acquired with the tapaccording to a weighting coefficient associated with the tap; andoutputting, from one of at least m evaluation circuits, each evaluationcircuit associated with a respective one of the at least m filters, asum of signal samples modulated by the taps of the associated filter inresponse to one of the m control signals associated with a signal periodother than the signal periods according to which the signal samples wereacquired.
 20. A method according to claim 19, wherein n is a sum of anumber of signal periods for an evaluation circuit to output the sum ofweighted signal samples and a number of signal periods to acquire asignal sample.
 21. A method according to claim 19, wherein a weightingcoefficient associated with one tap of one of the at least m filters isassociated with one tap of each other of the at least m filters.
 22. Amethod according to claim 19, wherein a control signal to be received byone tap of one of the at least m filters is to be received by one tap ofeach other of the at least m filters.
 23. A method according to claim19, wherein each of the m evaluation circuits is associated with arespective one of the m control signals.
 24. A method comprising:generating m control signals, each of the m control signals associatedwith a respective signal period; acquiring, with each of at least mweighting circuits, each of the at least m weighting circuits associatedwith a respective one of the m control signals, a signal sampleaccording to a signal period associated with the respective one of the mcontrol signals; modulating, with each of m-n weighting units of one ofthe at least m weighting circuits, the acquired signal sample accordingto a weighting coefficient associated with the weighting unit;receiving, with each of at least m evaluation circuits, one weightedsignal sample from each of m-n weighting circuits; and outputting a sumof the received weighted signal samples in response to one of the mcontrol signals associated with a signal period other than the signalperiods according to which the signal samples were acquired.
 25. Amethod according to claim 24, wherein each of the at least m weightingcircuits comprises a voltage sampler, a voltage-to-current convertercoupled to the voltage sampler, a current mirror coupled to thevoltage-to-current converter, and m-n weighting units coupled to thecurrent mirror, and further comprising: receiving, with each of the m-nweighting units, a substantially identical signal sample from thecurrent mirror; and modulating, with each of the m-n weighting units,the signal sample with an associated weighting coefficient.
 26. A systemcomprising: a chipset; and a die comprising a microprocessor incommunication with the chipset, wherein the microprocessor includes afilter comprising: a phase generator to generate m control signals, eachof the m control signals associated with a respective signal period; atleast m filters, each of the at least m filters comprising m-n taps,each of the m-n taps to receive one of the m control signals, to acquirea signal sample according to a signal period associated with thereceived control signal, and to modulate the signal sample according toa weighting coefficient associated with the tap; and at least mevaluation circuits, each circuit associated with a respective one ofthe at least m filters and to output a sum of signal samples modulatedby the taps of the associated filter in response to one of the m controlsignals associated with a signal period other than the signal periodsaccording to which the signal samples were acquired.
 27. A systemaccording to claim 26, wherein in the case of a first control signal,one tap of each of m-n of the at least m filters is to receive the firstcontrol signal, to acquire a first signal sample according to a firstsignal period associated with the first control signal, and to modulatethe first signal sample according to a weighting coefficient associatedwith the one tap.
 28. A system according to claim 27, wherein anevaluation circuit of one of the remaining n filters is to receive thefirst control signal and to output a first sum of weighted signalsamples in response to the first control signal.
 29. A systemcomprising: a chipset; and a die comprising a microprocessor incommunication with the chipset, wherein the microprocessor includes afilter comprising: a phase generator to generate m control signals, eachof the m control signals associated with a respective signal period; atleast m weighting circuits, each of the at least m weighting circuitsassociated with a respective one of the m control signals, to acquire asignal sample according to a signal period associated with therespective one of the m control signals, and comprising m-n weightingunits, each of the m-n weighting units of one of the at least mweighting circuits to modulate the acquired signal sample according to aweighting coefficient associated with the weighting unit; and at least mevaluation circuits, each evaluation circuit to receive one weightedsignal sample from m-n weighting circuits and to output a sum of thereceived signal samples in response to one of the m control signalsassociated with a signal period other than the signal periods accordingto which the signal samples were acquired.
 30. A system according toclaim 29, wherein each of the at least m weighting circuits comprises avoltage sampler, a voltage-to-current converter coupled to the voltagesampler, a current mirror coupled to the voltage-to-current converter,and m-n weighting units coupled to the current mirror, each of the m-nweighting units to receive a substantially identical signal sample fromthe current mirror and to multiply the signal sample by an associatedweighting coefficient.